A High-Density NAND EEPROM with Block-Page Programming for Microcomputer Applications

Yoshihisa Iwata, Masaki Momodomi, Tomoharu Tanaka, Hideko Oodaira, Yasuo Itoh, Ryozo Nakayama, Ryouhei Kirisawa, Seiichi Aritome, Tetsuo Endoh, Shirota Riichiro, Kazunori Ohuchi, Fuji Masuoka

Research output: Contribution to journalArticlepeer-review

16 Scopus citations

Abstract

A 5-V-only CMOS 4-Mb NAND EEPROM with high-speed block-page programming circuits and on-chip test circuits for evaluating the NAND-structured cell is described. This high-density EEPROM has successfully demonstrated the applicability of these techniques for micro-computer applications, which require a large nonvolatile memory system with low power consumption. 0018-9200/90/0400-0417$01.00

Original languageEnglish
Pages (from-to)417-424
Number of pages8
JournalIEEE Journal of Solid-State Circuits
Volume25
Issue number2
DOIs
StatePublished - 1 Jan 1990

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