A high density NAND EEPROM with block-page programming for microcomputer applications

Masaki Momodomi*, Yoshihisa Iwata, Tomoharu Tanaka, Yasuo Itoh, Shirota Riichiro, Fujio Masuoka

*Corresponding author for this work

Research output: Contribution to journalConference article

3 Scopus citations

Abstract

A 5V-only CMOS 4Mb NAND EEPROM with high-speed block-page programming circuits and on-chip test circuits for evaluating the NAND structured cell is described. This high density EEPROM has successfully demonstrated the applicability of these techniques for microcomputer applications which require a large non-volatile memory system with low power consumption.

Original languageEnglish
Article number5726193
JournalProceedings of the Custom Integrated Circuits Conference
DOIs
StatePublished - 1 Dec 1989
Event11th IEEE 1989 Custom Integrated Circuits Conference, CICC'89 - San Diego, CA, United States
Duration: 15 May 198918 May 1989

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