A 5V-only CMOS 4Mb NAND EEPROM with high-speed block-page programming circuits and on-chip test circuits for evaluating the NAND structured cell is described. This high density EEPROM has successfully demonstrated the applicability of these techniques for microcomputer applications which require a large non-volatile memory system with low power consumption.
|Journal||Proceedings of the Custom Integrated Circuits Conference|
|State||Published - 1 Dec 1989|
|Event||11th IEEE 1989 Custom Integrated Circuits Conference, CICC'89 - San Diego, CA, United States|
Duration: 15 May 1989 → 18 May 1989