In this work components of the next generation 0.10 μm CMOS technology are presented. They form the core of a platform encompassing logic, non volatile memory, and analog blocks. High performance bulk devices use 18 Å gate oxide (24 Å inversion Tox) while low power devices use 25 Å gate oxide (31 Å inversion Tox) for reduced gate leakage. Gate lengths range from 65 nm for the high performance devices to 90nm for the low power devices. Both 3.3V and 2.5V I/Os are supported using 70 Å and 50 Å oxide devices. The backend employs low-k (k ∼ 3) dielectric with multiple levels of Cu metallization. The high density 6T SRAM cell size is 1.33 μm2.
|Number of pages||4|
|Journal||Technical Digest - International Electron Devices Meeting|
|State||Published - 2001|
|Event||IEEE International Electron Devices Meeting IEDM 2001 - Washington, DC, United States|
Duration: 2 Dec 2001 → 5 Dec 2001