A high density 0.10μm CMOS technology using low k dielectric and copper interconnect

S. Parihar, M. Angyal*, B. Boeck, D. Reber, A. Singhal, T. Van Gompel, R. Li, B. Wilson, M. Wright, J. Chen, P. Grudowski, Y. Jeon, W. Qi, X. Bai, L. Parker, K. Strozewski, D. Smith, S. Roling, T. Sparks, T. StephensF. Huang, R. Mora, M. Aminpur, K. Hellig, L. Vishnubhotla, Y. Solomentsev, V. Arunachalam, A. Phillips, K. Junker, S. Filipiak, N. Ramani, M. Turner, M. Rendon, J. Molloy, K. McGuffin, A. Michel, R. Pena, D. Rose, J. Schmidt, M. Smith, M. Wilson, L. Terpolilli, P. Le, J. Sun, R. Ross, K. Yu, M. Hall, P. Ingersoll, M. Woo, G. Yeap, C. Lage

*Corresponding author for this work

Research output: Contribution to journalConference articlepeer-review

18 Scopus citations

Abstract

In this work components of the next generation 0.10 μm CMOS technology are presented. They form the core of a platform encompassing logic, non volatile memory, and analog blocks. High performance bulk devices use 18 Å gate oxide (24 Å inversion Tox) while low power devices use 25 Å gate oxide (31 Å inversion Tox) for reduced gate leakage. Gate lengths range from 65 nm for the high performance devices to 90nm for the low power devices. Both 3.3V and 2.5V I/Os are supported using 70 Å and 50 Å oxide devices. The backend employs low-k (k ∼ 3) dielectric with multiple levels of Cu metallization. The high density 6T SRAM cell size is 1.33 μm2.

Original languageEnglish
Pages (from-to)249-252
Number of pages4
JournalTechnical Digest - International Electron Devices Meeting
DOIs
StatePublished - 2001
EventIEEE International Electron Devices Meeting IEDM 2001 - Washington, DC, United States
Duration: 2 Dec 20015 Dec 2001

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