A High Current efficiency Stacked Digital Low Dropout Array with True-Random-Noise Injection and Ultralow Output Ripple for Power-Side Channel Attack Protection

Cheng Yen Lee, Tzu Ping Huang, Ke Horng Chen, Ying Hsi Lin, Shian Ru Lin, Tsung Yen Tsai

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

This paper proposes a stacked digital low dropout (DLDO) array with three stacked groups to improve security and efficiency, consuming 1/3 of the input current in the prior art. The security is improved by two mechanisms. The advanced encryption standard (AES) engine can be one of point of loads (POLs) hidden in the deeper levels to minimize the disturbance from the AES to the input current. The other is the digital balanced interleave control (DBIC) receives random sources from internal leakage current frequency generator (LCFG) to generate randomly noise current to further hide the current interference caused by the AES. Due to DBIC and LCFG techniques, the correlation between input current and AES current is low to 0.006, which is 150 times lower than that of conventional DLDO.

Original languageEnglish
Title of host publication2019 Symposium on VLSI Circuits, VLSI Circuits 2019 - Digest of Technical Papers
PublisherInstitute of Electrical and Electronics Engineers Inc.
PagesC322-C323
ISBN (Electronic)9784863487185
DOIs
StatePublished - Jun 2019
Event33rd Symposium on VLSI Circuits, VLSI Circuits 2019 - Kyoto, Japan
Duration: 9 Jun 201914 Jun 2019

Publication series

NameIEEE Symposium on VLSI Circuits, Digest of Technical Papers
Volume2019-June

Conference

Conference33rd Symposium on VLSI Circuits, VLSI Circuits 2019
CountryJapan
CityKyoto
Period9/06/1914/06/19

Fingerprint Dive into the research topics of 'A High Current efficiency Stacked Digital Low Dropout Array with True-Random-Noise Injection and Ultralow Output Ripple for Power-Side Channel Attack Protection'. Together they form a unique fingerprint.

Cite this