A high clock-offset tolerance for DSSS synchronization

Hsuan Yu Liu, Shuenn Der Tzeng, Yi Chuan Liu, Chung Cheng Wang, Terng Ren Hsu, Terng-Yin Hsu, Chen-Yi Lee

Research output: Contribution to journalArticlepeer-review

Abstract

A dynamic ADC sampling methodology based on error-tracking loop is proposed in this paper to improve synchronized performance in DSSS baseband transceivers. To maintain the synchronized performance the ADC sampling rate is controlled by error-tracking loop to let clock offset becomes lower. For 1.8MHz clock offset based on 44MHz ADC sampling rate the BER of DSSS baseband transceivers can achieve 10-5 in AWGN channel.

Original languageEnglish
Pages (from-to)944-946
Number of pages3
JournalMidwest Symposium on Circuits and Systems
Volume2
DOIs
StatePublished - 1 Jan 2000

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