TY - JOUR
T1 - A hierarchical criticality-aware architectural synthesis framework for multicycle communication
AU - Chen, Chia I.
AU - Huang, Juinn-Dar
PY - 2010/1/1
Y1 - 2010/1/1
N2 - In deep submicron era, wire delay is no longer negligible and is becoming a dominant factor of the system performance. To cope with the increasing wire delay, several state-of-the-art architectural synthesis flows have been proposed for the distributed register architectures by enabling on-chip multicycle communication. In this article, we present a new performance-driven criticality-aware synthesis framework CriAS targeting regular distributed register architectures. To achieve high system performance, CriAS features a hierarchical binding-then-placement for minimizing the number of performance-critical global data transfers. The key ideas are to take time criticality as the major concern at earlier binding stages before the detailed physical placement information is available, and to preserve the locality of closely related critical components in the later placement phase. The experimental results show that CriAS can achieve an average of 14.26% overall performance improvement with no runtime overhead as compared to the previous art.
AB - In deep submicron era, wire delay is no longer negligible and is becoming a dominant factor of the system performance. To cope with the increasing wire delay, several state-of-the-art architectural synthesis flows have been proposed for the distributed register architectures by enabling on-chip multicycle communication. In this article, we present a new performance-driven criticality-aware synthesis framework CriAS targeting regular distributed register architectures. To achieve high system performance, CriAS features a hierarchical binding-then-placement for minimizing the number of performance-critical global data transfers. The key ideas are to take time criticality as the major concern at earlier binding stages before the detailed physical placement information is available, and to preserve the locality of closely related critical components in the later placement phase. The experimental results show that CriAS can achieve an average of 14.26% overall performance improvement with no runtime overhead as compared to the previous art.
KW - Architectural synthesis
KW - Criticality-driven
KW - High-level synthesis
KW - Multicycle communication
KW - Performance-driven
UR - http://www.scopus.com/inward/record.url?scp=78049315842&partnerID=8YFLogxK
U2 - 10.1587/transfun.E93.A.1300
DO - 10.1587/transfun.E93.A.1300
M3 - Article
AN - SCOPUS:78049315842
VL - E93-A
SP - 1300
EP - 1308
JO - IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
JF - IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
SN - 0916-8508
IS - 7
ER -