A hierarchical criticality-aware architectural synthesis framework for multicycle communication

Chia I. Chen*, Juinn-Dar Huang

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

4 Scopus citations


In deep submicron era, wire delay is no longer negligible and is becoming a dominant factor of the system performance. To cope with the increasing wire delay, several state-of-the-art architectural synthesis flows have been proposed for the distributed register architectures by enabling on-chip multicycle communication. In this article, we present a new performance-driven criticality-aware synthesis framework CriAS targeting regular distributed register architectures. To achieve high system performance, CriAS features a hierarchical binding-then-placement for minimizing the number of performance-critical global data transfers. The key ideas are to take time criticality as the major concern at earlier binding stages before the detailed physical placement information is available, and to preserve the locality of closely related critical components in the later placement phase. The experimental results show that CriAS can achieve an average of 14.26% overall performance improvement with no runtime overhead as compared to the previous art.

Original languageEnglish
Pages (from-to)1300-1308
Number of pages9
JournalIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Issue number7
StatePublished - 1 Jan 2010


  • Architectural synthesis
  • Criticality-driven
  • High-level synthesis
  • Multicycle communication
  • Performance-driven

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