@inproceedings{e161a1814f804d2aad45a33228b6fcd9,
title = "A hierarchical analysis methodology for chip-level power delivery with realizable model reduction",
abstract = "In this paper, we propose a novel hierarchical analysis methodology to facilitate efficient chip-level power fluctuation analysis. With extreme efficiency and simplicity, our design methodology first builds time-varying multiport Norton equivalent circuits in a row-by-row or block-by-block basis, followed by global analysis of the integrated reduced models. After generating the Norton equivalent sources at external ports, we apply realizable model order reduction technologies to further reduce the model. Since the elements of our reduced model are also RC devices, they are fully compatible with general circuit simulation engines. The experimental results demonstrate more than 4X speed up with the flat simulation while maintaining within 5% accuracy.",
author = "Yu-Min Lee and {Chung-Ping Chen}, C.",
year = "2003",
month = jan,
day = "1",
doi = "10.1109/ASPDAC.2003.1195098",
language = "English",
series = "Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "614--618",
booktitle = "Proceedings of the ASP-DAC 2003 Asia and South Pacific Design Automation Conference",
address = "United States",
note = "null ; Conference date: 21-01-2003 Through 24-01-2003",
}