A hierarchical analysis methodology for chip-level power delivery with realizable model reduction

Yu-Min Lee; C. Chung-Ping Chen

doi:10.1109/ASPDAC.2003.1195098

A hierarchical analysis methodology for chip-level power delivery with realizable model reduction

Yu-Min Lee, C. Chung-Ping Chen

Department of Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

In this paper, we propose a novel hierarchical analysis methodology to facilitate efficient chip-level power fluctuation analysis. With extreme efficiency and simplicity, our design methodology first builds time-varying multiport Norton equivalent circuits in a row-by-row or block-by-block basis, followed by global analysis of the integrated reduced models. After generating the Norton equivalent sources at external ports, we apply realizable model order reduction technologies to further reduce the model. Since the elements of our reduced model are also RC devices, they are fully compatible with general circuit simulation engines. The experimental results demonstrate more than 4X speed up with the flat simulation while maintaining within 5% accuracy.

Original language	English
Title of host publication	Proceedings of the ASP-DAC 2003 Asia and South Pacific Design Automation Conference
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	614-618
Number of pages	5
ISBN (Electronic)	0780376595
DOIs	https://doi.org/10.1109/ASPDAC.2003.1195098
State	Published - 1 Jan 2003
Event	Asia and South Pacific Design Automation Conference, ASP-DAC 2003 - Kitakyushu, Japan Duration: 21 Jan 2003 → 24 Jan 2003

Publication series

Name	Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
Volume	2003-January

Conference

Conference	Asia and South Pacific Design Automation Conference, ASP-DAC 2003
Country	Japan
City	Kitakyushu
Period	21/01/03 → 24/01/03

Access to Document

10.1109/ASPDAC.2003.1195098

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Lee, Y-M., & Chung-Ping Chen, C. (2003). A hierarchical analysis methodology for chip-level power delivery with realizable model reduction. In Proceedings of the ASP-DAC 2003 Asia and South Pacific Design Automation Conference (pp. 614-618). [1195098] (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; Vol. 2003-January). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ASPDAC.2003.1195098

Lee, Yu-Min ; Chung-Ping Chen, C. / A hierarchical analysis methodology for chip-level power delivery with realizable model reduction. Proceedings of the ASP-DAC 2003 Asia and South Pacific Design Automation Conference. Institute of Electrical and Electronics Engineers Inc., 2003. pp. 614-618 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

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abstract = "In this paper, we propose a novel hierarchical analysis methodology to facilitate efficient chip-level power fluctuation analysis. With extreme efficiency and simplicity, our design methodology first builds time-varying multiport Norton equivalent circuits in a row-by-row or block-by-block basis, followed by global analysis of the integrated reduced models. After generating the Norton equivalent sources at external ports, we apply realizable model order reduction technologies to further reduce the model. Since the elements of our reduced model are also RC devices, they are fully compatible with general circuit simulation engines. The experimental results demonstrate more than 4X speed up with the flat simulation while maintaining within 5% accuracy.",

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Lee, Y-M & Chung-Ping Chen, C 2003, A hierarchical analysis methodology for chip-level power delivery with realizable model reduction. in Proceedings of the ASP-DAC 2003 Asia and South Pacific Design Automation Conference., 1195098, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, vol. 2003-January, Institute of Electrical and Electronics Engineers Inc., pp. 614-618, Asia and South Pacific Design Automation Conference, ASP-DAC 2003, Kitakyushu, Japan, 21/01/03. https://doi.org/10.1109/ASPDAC.2003.1195098

A hierarchical analysis methodology for chip-level power delivery with realizable model reduction. / Lee, Yu-Min; Chung-Ping Chen, C.

Proceedings of the ASP-DAC 2003 Asia and South Pacific Design Automation Conference. Institute of Electrical and Electronics Engineers Inc., 2003. p. 614-618 1195098 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; Vol. 2003-January).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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Lee Y-M, Chung-Ping Chen C. A hierarchical analysis methodology for chip-level power delivery with realizable model reduction. In Proceedings of the ASP-DAC 2003 Asia and South Pacific Design Automation Conference. Institute of Electrical and Electronics Engineers Inc. 2003. p. 614-618. 1195098. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC). https://doi.org/10.1109/ASPDAC.2003.1195098