A hardware implementation in FPGA of the Rijndael algorithm

Cristian Chiţu; David Chien; Charles Chien; Ingrid Verbauwhede; Mau-Chung Chang

doi:10.1109/MWSCAS.2002.1187269

A hardware implementation in FPGA of the Rijndael algorithm

Cristian Chiţu^*, David Chien, Charles Chien, Ingrid Verbauwhede, Mau-Chung Chang

^*Corresponding author for this work

Department of Electronics Engineering

Research output: Contribution to conference › Paper › peer-review

17 Scopus citations

Abstract

Implementation in FPGA of the new Advanced Encryption Standard, Rijndael, was developed and experimentally tested using the Insight Development Kit board, based on Xilinx Virtex II XC2V1000-4 device. The experimental clock frequency was equal to 75 MHz and translates to the throughputs of 739 Mbit/s for Rijndael with block size and key size of 128 bits, respectively. This circuit has capability to handle encryption/decryption and fitted in one FPGA taking approximately 84% of the area. Our work supplements and extends other research efforts [1] [2].

Original language	English
DOIs	https://doi.org/10.1109/MWSCAS.2002.1187269
State	Published - 1 Dec 2002
Event	2002 45th Midwest Symposium on Circuits and Systems - Tulsa, OK, United States Duration: 4 Aug 2002 → 7 Aug 2002

Conference

Conference	2002 45th Midwest Symposium on Circuits and Systems
Country	United States
City	Tulsa, OK
Period	4/08/02 → 7/08/02

Access to Document

10.1109/MWSCAS.2002.1187269

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AU - Chiţu, Cristian

AU - Chien, David

AU - Chien, Charles

AU - Verbauwhede, Ingrid

AU - Chang, Mau-Chung

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N2 - Implementation in FPGA of the new Advanced Encryption Standard, Rijndael, was developed and experimentally tested using the Insight Development Kit board, based on Xilinx Virtex II XC2V1000-4 device. The experimental clock frequency was equal to 75 MHz and translates to the throughputs of 739 Mbit/s for Rijndael with block size and key size of 128 bits, respectively. This circuit has capability to handle encryption/decryption and fitted in one FPGA taking approximately 84% of the area. Our work supplements and extends other research efforts [1] [2].

AB - Implementation in FPGA of the new Advanced Encryption Standard, Rijndael, was developed and experimentally tested using the Insight Development Kit board, based on Xilinx Virtex II XC2V1000-4 device. The experimental clock frequency was equal to 75 MHz and translates to the throughputs of 739 Mbit/s for Rijndael with block size and key size of 128 bits, respectively. This circuit has capability to handle encryption/decryption and fitted in one FPGA taking approximately 84% of the area. Our work supplements and extends other research efforts [1] [2].

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