A hardware implementation in FPGA of the Rijndael algorithm

Cristian Chiţu*, David Chien, Charles Chien, Ingrid Verbauwhede, Mau-Chung Chang

*Corresponding author for this work

Research output: Contribution to conferencePaperpeer-review

17 Scopus citations

Abstract

Implementation in FPGA of the new Advanced Encryption Standard, Rijndael, was developed and experimentally tested using the Insight Development Kit board, based on Xilinx Virtex II XC2V1000-4 device. The experimental clock frequency was equal to 75 MHz and translates to the throughputs of 739 Mbit/s for Rijndael with block size and key size of 128 bits, respectively. This circuit has capability to handle encryption/decryption and fitted in one FPGA taking approximately 84% of the area. Our work supplements and extends other research efforts [1] [2].

Original languageEnglish
DOIs
StatePublished - 1 Dec 2002
Event2002 45th Midwest Symposium on Circuits and Systems - Tulsa, OK, United States
Duration: 4 Aug 20027 Aug 2002

Conference

Conference2002 45th Midwest Symposium on Circuits and Systems
CountryUnited States
CityTulsa, OK
Period4/08/027/08/02

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