A hardware-efficient VLSI implementation of a 4-channel ICA processor for biomedical signal measurement

Chiu Kuo Chen*, Ericson Chua, Chih Chung Fu, Shao Yen Tseng, Wai-Chi  Fang

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

7 Scopus citations

Abstract

This paper presents a 4-channel ICA implementation in the separation of EEG signals for on-line monitoring and analysis of brain functionalities. A novel ICA architecture utilizing mixed sequential, pipelined, and parallel processing units and employing interleaved and circular-based RAM modules to achieve hardware-efficient design is presented. The ICA processor is fabricated using UMC 90nm High-Vt CMOS technology.

Original languageEnglish
Title of host publication2011 IEEE International Conference on Consumer Electronics, ICCE 2011
Pages607-608
Number of pages2
DOIs
StatePublished - 28 Mar 2011
Event2011 IEEE International Conference on Consumer Electronics, ICCE 2011 - Las Vegas, NV, United States
Duration: 9 Jan 201112 Jan 2011

Publication series

NameDigest of Technical Papers - IEEE International Conference on Consumer Electronics
ISSN (Print)0747-668X

Conference

Conference2011 IEEE International Conference on Consumer Electronics, ICCE 2011
CountryUnited States
CityLas Vegas, NV
Period9/01/1112/01/11

Fingerprint Dive into the research topics of 'A hardware-efficient VLSI implementation of a 4-channel ICA processor for biomedical signal measurement'. Together they form a unique fingerprint.

Cite this