A hardware-efficient H.264/AVC motion-estimation design for high-definition video

Yu Kun Lin*, Chia Chun Lin, Tzu Yun Kuo, Tian-Sheuan Chang

*Corresponding author for this work

Research output: Contribution to journalArticle

54 Scopus citations

Abstract

Motion estimation (ME) in high-definition H.264 video coding presents a significant design challenge for memory bandwidth, latency, and cost because of its large search range and various modes. To conquer this problem, this paper presents a low-latency and hardware-efficient ME design with three design techniques. The first technique on integer-pel ME (IME) adopts parallel instead of serial multiresolution search so that we can process 1080 @ p 60 fps videos with ±128 search range within just 256 cycles, 5.95-KB buffers, and 213.7K gates. The second technique on fractional-pel ME (FME) uses a single-iteration six-point search to reduce the cycle count by half with similar gate count and negligible quality loss. The third technique applies a mode-filtering approach to further reduce the bandwidth and cycles and share the buffer of IME and FME. The final ME implementation with 0.13-μm process can support processing of 1080 p 60 fps with just 128.8 MHz, 282.6 K gates, and 8.54-KB buffer, which saves 60% gate count, and 68.9% SRAM buffers when compared with the previous design.

Original languageEnglish
Pages (from-to)1526-1535
Number of pages10
JournalIEEE Transactions on Circuits and Systems I: Regular Papers
Volume55
Issue number6
DOIs
StatePublished - 1 Jul 2008

Keywords

  • Digital circuits
  • H.264
  • High-definition television (HDTV)
  • Motion estimation (ME)
  • Video coding
  • Video signal processing

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