A H.264 basic-unit level rate control algorithm facilitating hardware realization

Ping Tsung Wu*, Tzu Chun Chang, Ching Lung Su, Jiun-In  Guo

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

5 Scopus citations

Abstract

Rate Control plays an important role for video coding especially in video streaming applications with bandwidth constraints. The inherent sequential processing in H.264 basic unit (BU) level rate control algorithm makes it hard to be realized in a pipelined H.264 hardware encoder without increasing the processing latency. In this paper we propose a new H.264 BU-level rate control algorithm facilitating hardware realization. The proposed algorithm breaks down the sequential processing dependence in the original rate control algorithm in JM and reduces 28% for QCIF, 66% for CIF, 87% for D1 of hardware cycles while maintaining good video quality. Simulation results shows that the proposed algorithm reduces MAD's memory buffer size to be Nunit * 14bits, which amounts to 26% for QCIF, 59% for CIF, 83% for D1 reduction as compared to JM rate control. Moreover, the proposed algorithm possesses high feasibility for hardware realization.

Original languageEnglish
Title of host publication2008 IEEE International Conference on Acoustics, Speech and Signal Processing, ICASSP
Pages2185-2188
Number of pages4
DOIs
StatePublished - 16 Sep 2008
Event2008 IEEE International Conference on Acoustics, Speech and Signal Processing, ICASSP - Las Vegas, NV, United States
Duration: 31 Mar 20084 Apr 2008

Publication series

NameICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings
ISSN (Print)1520-6149

Conference

Conference2008 IEEE International Conference on Acoustics, Speech and Signal Processing, ICASSP
CountryUnited States
CityLas Vegas, NV
Period31/03/084/04/08

Keywords

  • BU Level
  • H.264
  • Rate control

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