This paper presents a high-throughput FFT processor for IEEE 802.15.3c (WPANs) standard. To meet the 2.59 Giga-sample/s throughput requirements, radix-16 FFT algorithm is adopted and reformulated to an efficient form so that the required number of butterfly stages is reduced and the proposed radix-16 FFT butterfly processing element (PE) can be optimally pipelined. Specifically, the radix-16 butterfly PE consists of one radix-4 and two radix-2 cascaded pipelined butterfly units. It facilitates low-complexity realization of radix-16 butterfly operation and high operation speed due to the optimized pipelined structure. Hardware reuse and low-power schemes are also devised to reduce both area and power consumption. Moreover, a multibank memory scheme is used to support up to 16-times I/O capability of a single-bank memory, which can greatly reduce the input/output time of FFT data samples. As a result, the proposed radix-16 FFT processor is area-efficient with high data processing rate and hardware utilization efficiency. The EDA synthesis results show that the proposed design has 2.59 GS/s throughput and it consumes 103.5 mW by using UMC 90nm process.