In this paper, we extend our generalized methodology for designing a lower-error and area-time efficient 2's-complement fixed-width Booth multiplier that receives two n-bit numbers and produces an n-bit product. The generalized methodology involving three steps results in several better error-compensation biases. These better error-compensation biases can be mapped to low-error fixed-width Booth multipliers suitable for VLSI implementation. Finally, we successfully apply the proposed fixed-width Booth multipliers to speech signal processing. The simulation results show that the performance is superior to that using the direct-truncation fixed-width Booth multiplier.
|Journal||Midwest Symposium on Circuits and Systems|
|State||Published - 1 Dec 2004|
|Event||The 2004 47th Midwest Symposium on Circuits and Systems - Conference Proceedings - Hiroshima, Japan|
Duration: 25 Jul 2004 → 28 Jul 2004