A fully-parallel step-by-step BCH decoder over composite field for NOR flash memories

Yi Hsun Chen*, Chi Heng Yang, Hsie-Chia Chang

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Scopus citations

Abstract

This paper presents a (274,256,2) DEC BCH decoder for NOR flash memories to improve the reliability. From the step-by-step algorithm, the decoding mechanism can be derived from a simple checking equation and its fully-parallel architecture is implemented to meet the low latency requirement. Moreover, the composite field arithmetic without extra field conversion hardware is applied to the whole decoder for further reducing complexity. By using UMC 90 nm CMOS technology, the synthesis results show that the latency is 2.5 ns with 23.2K logic gates.

Original languageEnglish
Title of host publication2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers
DOIs
StatePublished - 25 Jul 2012
Event2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Hsinchu, Taiwan
Duration: 23 Apr 201225 Apr 2012

Publication series

Name2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers

Conference

Conference2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012
CountryTaiwan
CityHsinchu
Period23/04/1225/04/12

Keywords

  • BCH codes
  • Composite field
  • Double-Error-Correcting
  • NOR flash memories
  • Step-by-step decoding algorithm

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    Chen, Y. H., Yang, C. H., & Chang, H-C. (2012). A fully-parallel step-by-step BCH decoder over composite field for NOR flash memories. In 2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers [6212602] (2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers). https://doi.org/10.1109/VLSI-DAT.2012.6212602