This paper demonstrates a fully integrated builtin self-test (BIST) Σ-Δ ADC in 0.18-μm CMOS that can be wirelessly tested on a wireless test platform. The ADC under test (AUT) is a second-order Σ-Δ modulator which employs the decorrelating design-for-digital- testability (D 3T) scheme to make itself digitally testable. The proposed BIST design is based on the modified controlled sine wave fitting (CSWF) method. It generates the required digital stimuli for the AUT and analyze the responses of the AUT in time domain. The BIST circuitry conducts standard single-tone functional tests for measuring the signal-to-noise-and-distortion ratio (SNDR), the dynamic range, the offset, and the gain error of the AUT. The hardware overhead of the purely digital BIST circuits are only 9.9k gates. The prototype was tested on the HOY wireless test platform. The HOY wireless test platform provides user-friendly design-fortestability and test environment including hardware and software. The ultimate goal of the platform is to eliminate the need of accessing I/O pins of the chips during testing so as to address the difficulty and the high cost of testing high-pin-count mixedsignal ICs. Measurements of the BIST ADC show that the peak SNDR and the dynamic range are 78.6 dB and 86 dB respectively. The tested passband of the AUT using the BIST is about 17 kHz which is pretty close to the rated 20-kHz passband of the AUT.