A fully integrated built-in self-test Σ-Δ ADC based on the modified controlled sine-wave fitting procedure

Hao-Chiao Hong*, Fang Yi Su, Shao Feng Hung

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

15 Scopus citations


This paper demonstrates the first fully integrated built-in self-test (BIST) Σ-Δ analog-to-digital converter (ADC) chip to the best of our knowledge. The ADC under test (AUT) comprises a second-order design-for-digital-testability Σ-Δ modulator and a decimation filter. The purely digital BIST circuitry conducts single-tone tests for the signal-to-noise-and-distortion ratio (SNDR), the dynamic range, the offset, and the gain error of the AUT. The BIST design is based on the proposed modified controlled sine-wave fitting procedure to address the component overload issues, reduce the setup parameter numbers, and eliminate the need for parallel multipliers. The total gate count of the whole BIST circuitry is only 13300. The hardware overhead is much less than the BIST design using the traditional fast Fourier transform (FFT) analysis. Measurement results show that the peak SNDR results of the proposed BIST design and the conventional FFT analysis are 75.5 and 75.3 dB, respectively. The subtle SNDR difference is already within analog test uncertainty. The BIST Σ-Δ ADC achieves a digital test bandwidth higher than 17 kHz, very close to the rated 20-kHz bandwidth of the AUT.

Original languageEnglish
Article number5353704
Pages (from-to)2334-2344
Number of pages11
JournalIEEE Transactions on Instrumentation and Measurement
Issue number9
StatePublished - 1 Sep 2010


  • Σ-Δ modulation
  • Analog-to-digital conversion (ADC)
  • built-in self-test (BIST)
  • design for testability
  • integrated circuit testing
  • mixed analogdigital integrated circuits

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