In this paper, a framework of designing a low-error and power-efficient two's-complement fixed-width Booth multiplier that receives two n-bit numbers and produces an n-bit product is proposed. The design methodology of the framework involving four steps results in one better errorcompensation bias. The better error-compensation bias can be mapped to a simple low-error fixed-width Booth multiplier with a little penalty of power consumption. For the benchmark of 8x8 multipliers, the simulation results show that a reduction of 82.04% average error compared to that using the direct-truncated fixed-width Booth multiplier can be obtained. Moreover, the power consumption can be saved 40.68% compared to that of full-precision Booth multiplier design.
|Number of pages||4|
|Journal||Proceedings - IEEE International Symposium on Circuits and Systems|
|State||Published - 1 Dec 2005|
|Event||IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005 - Kobe, Japan|
Duration: 23 May 2005 → 26 May 2005