A compact, low power and global-mismatch-tolerant 0.86 GHz fractional-N PLL is designed to cover IEEE 802.11abg, PCS/DCS and cellular bands. Two new techniques are proposed to cancel the in-band quantization noise and fractional spurs. Firstly, a second order binary-weighted digital/analog differentiator (DAD) is utilized to enable the second order mismatch shaping and reduce the quantization noise by 25 dB, along with advantages of compact circuit implementation with smaller routing area and less power consumption over those of dynamic element matching (DEM) based counterparts. Secondly, mechanisms causing fractional spurs are also identified and a third order offset-frequency delta-sigma (Δ Σ) modulator is devised to decrease the in-band spurs by 20 dB in simulation and 8 dB in present single-ended circuit implementation.
- Binary-weighted digital-analog differentiator (DAD)
- Delta-sigma modulation
- Digital-analog conversion
- Mismatch shaping
- Multiband frequency synthesizer
- Offset-frequency delta-sigma (Δ Σ) modulator
- Phase-locked loop (PLL)