A floating well method for exact capacitance-voltage measurement of nano technology

Hung Der Su*, Bi Shiou Chiou, Shien Yang Wu, Ming Hsung Chang, Kuo Hua Lee, Yung Shun Chen, Chih Ping Chao, Yee Chaung See, Jack Yuan Chen Sun

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

1 Scopus citations

Abstract

Small gate area with short gate length reduces the C-V distortion of ultrathin oxide devices, but results in high parasitic capacitance/total capacitance ratio. The floating well method can exclude the parasitic capacitance to obtain accurate inversion oxide thickness without using any dummy pattern. It is suitable for nano technology.

Original languageEnglish
Pages (from-to)1543-1544
Number of pages2
JournalIEEE Transactions on Electron Devices
Volume50
Issue number6
DOIs
StatePublished - Jun 2003

Keywords

  • Capacitance-voltage
  • Electrical oxide thickness
  • Floating well
  • Nano technology
  • Ultrathin oxide

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