A flash scheduling strategy for current capping in multi-power-mode SSDs

Li-Pin Chang, Chia Hsiang Cheng, Kai Hsiang Lin

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

2 Scopus citations

Abstract

Solid state disks (SSDs) employ internal parallelism for high throughput, but concurrent flash operations can draw a high instantaneous current. Due to power budgeting or powersource changing, SSDs could be forced into a new operation mode with a lower current supply limit. This study presents a flash scheduling algorithm to optimize the SSD internal parallelism subject to the current limit. Based on realistic flash current models, our scheduler decides the actual starting times of every flash operation, and it efficiently examines the peak current only at a few time points. Our experiments show that our approach outperformed existing methods, and its feasibility had been verified on the OpenSSD platform.

Original languageEnglish
Title of host publication2017 22nd Asia and South Pacific Design Automation Conference, ASP-DAC 2017
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages566-571
Number of pages6
ISBN (Electronic)9781509015580
DOIs
StatePublished - 16 Feb 2017
Event22nd Asia and South Pacific Design Automation Conference, ASP-DAC 2017 - Chiba, Japan
Duration: 16 Jan 201719 Jan 2017

Publication series

NameProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Conference

Conference22nd Asia and South Pacific Design Automation Conference, ASP-DAC 2017
CountryJapan
CityChiba
Period16/01/1719/01/17

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