A fast settling and low reference spur PLL with double sampling phase detector

Guo Jue Huang*, Che Sheng Chen, Wen Slien Wuen, Kuei-Ann Wen

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

This paper proposes a double sampling phase detector (DSPD) for the charge-pump phase-locked loop (PLL) design. The DSPD can double the PLL loop bandwidth to obtain the fast settling time and meanwhile shift the reference spur to higher frequency to suppress the reference spur. Verilog-AMS charge-pump PLL timing models with DSPD and conventional phase detector (PD) are developed to verify the fast settling time and low reference spur. By comparing the DSPD architecture to the conventional PD architecture, the settling time can be reduced 50% in the 30ppm frequency accuracy and the reference spur can be suppressed 5.9 dB.

Original languageEnglish
Title of host publicationProceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008
Pages316-319
Number of pages4
DOIs
StatePublished - 26 Dec 2008
Event15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008 - St. Julian's, Malta
Duration: 31 Aug 20083 Sep 2008

Publication series

NameProceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008

Conference

Conference15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008
CountryMalta
CitySt. Julian's
Period31/08/083/09/08

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