A fast prototyping framework for analog layout migration with planar preservation

Po Cheng Pan, Ching Yu Chin, Hung-Ming Chen, Tung Chieh Chen, Chin Chieh Lee, Jou Chun Lin

Research output: Contribution to journalArticlepeer-review

9 Scopus citations

Abstract

Analog layout generation in the advanced CMOS design is challenging by its increasing layout constraints and performance requirements. This situation becomes more intricate by the growing parasitic variability and manufacturing reliability. To facilitate the feasibility of template-based layout migration, this paper first introduces a layout preservation, which extracts placement and routing behaviors from an existing layout into a crossing graph via constrained Delaunay triangulation. And later this crossing graph can be migrated into multiple layouts with placement and routing reconnection. The proposed approach also provides a refinement for wire to optimize the performance metrics. This approach is applied to a variable-gain amplifier, a folded-cascode operational amplifier, and a low dropout regulator. The experimental results demonstrate more possibility on layout migration, such that averagely more than 75% routing of migrated layout is generated by our approach. Additionally, it exhibits the productivity with qualified performance on different designs.

Original languageEnglish
Article number7078859
Pages (from-to)1373-1386
Number of pages14
JournalIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Volume34
Issue number9
DOIs
StatePublished - 1 Sep 2015

Keywords

  • AMS circuit design
  • layout migration
  • low dropout regulator
  • placement & routing
  • prototyping
  • slicing tree
  • trangulation

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