We develop a parallel implementation of Feng-Rao algorithm (1993) with systolic array architecture by adopting a specially arranged syndrome matrix. The specially arranged syndrome matrix is in a nearly Hermitian or Hankel form. This parallel decoding architecture can correct up to i errors, where t is equal to half of the Feng-Rao bound, and has the time complexity (m+g+1) by using a series of (t+[(g-1)/2]+1) effective processors (or cells) and g trivial processors. The control circuit for the proposed systolic array architecture is quite simple and a circuit for performing the majority voting scheme is also developed. The proposed architecture without inclusion of the majority voting scheme requires totally t+[(g-1)/2] inversion circuits and (t+[(g-1)/2]) (t+1+[(g-1)/2])/2 multipliers. In a practical design, this hardware complexity is acceptable.