A fast-locking all-digital phased-locked loop with a 1 ps resolution time-to-digital converter using calibrated time amplifier and interpolation digitally-controlled-oscillator

Hsing Chien Chu, Yi Hsiang Hua, Chung-Chih Hung

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

3 Scopus citations

Abstract

This paper presents an all-digital phase-locked loop (ADPLL) in the 0.18 pm CMOS process, which uses a multi-stage time-to-digital converter (TDC) with calibration and interpolation digitally-controlled-oscillator (IDCO). The ADPLL also utilizes a frequency tracking engine (FTE) to reduce the system locking time. The ADPLL has a frequency range of 149-1450 MHz, the minimum peak-to-peak jitter achieves 21.9 ps, and the TDC shows the minimum resolution of 1 ps. The power dissipation of the ADPLL is 18.2 mW at 800 MHz.

Original languageEnglish
Title of host publication2016 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2016
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages375-378
Number of pages4
ISBN (Electronic)9781509018307
DOIs
StatePublished - 15 Dec 2016
Event2016 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2016 - Hong Kong, Hong Kong
Duration: 3 Aug 20165 Aug 2016

Publication series

Name2016 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2016

Conference

Conference2016 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2016
CountryHong Kong
CityHong Kong
Period3/08/165/08/16

Keywords

  • All-digital phase-locked loop (ADPLL)
  • digitally-controlled-oscillator (DCO)
  • time amplifier (TA)
  • time-to-digital converter (TDC)

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