A fast-locking all-digital phase locked loop in 90nm CMOS for Gigascale systems

Yi Wei Chen, Hao-Chiao Hong

Research output: Chapter in Book/Report/Conference proceedingConference contribution

8 Scopus citations

Abstract

This paper presents an all-digital phase locked loop (ADPLL) design that features fast frequency locking and a wide tuning range. The all-digital implementation makes the design well suit Gigascale systems in advanced technology. The proposed ADPLL first uses the Regula Falsi method to fast lock the output frequency. Then, a frequency tracking (FT) loop is enabled to stabilize the output frequency against environmental disturbance as conventional PLL does. A test chip has been fabricated in 90 nm CMOS. Measurement results show the proposed ADPLL locks in 7 cycles and provides output frequencies ranging from 460.1 MHz to 6.117 GHz.

Original languageEnglish
Title of host publication2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages1134-1137
Number of pages4
ISBN (Print)9781479934324
DOIs
StatePublished - 1 Jan 2014
Event2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014 - Melbourne, VIC, Australia
Duration: 1 Jun 20145 Jun 2014

Publication series

NameProceedings - IEEE International Symposium on Circuits and Systems
ISSN (Print)0271-4310

Conference

Conference2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014
CountryAustralia
CityMelbourne, VIC
Period1/06/145/06/14

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    Chen, Y. W., & Hong, H-C. (2014). A fast-locking all-digital phase locked loop in 90nm CMOS for Gigascale systems. In 2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014 (pp. 1134-1137). [6865340] (Proceedings - IEEE International Symposium on Circuits and Systems). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISCAS.2014.6865340