@inproceedings{99cf96e06cb6418dbf7913d58b767fd9,
title = "A fast-locking all-digital phase locked loop in 90nm CMOS for Gigascale systems",
abstract = "This paper presents an all-digital phase locked loop (ADPLL) design that features fast frequency locking and a wide tuning range. The all-digital implementation makes the design well suit Gigascale systems in advanced technology. The proposed ADPLL first uses the Regula Falsi method to fast lock the output frequency. Then, a frequency tracking (FT) loop is enabled to stabilize the output frequency against environmental disturbance as conventional PLL does. A test chip has been fabricated in 90 nm CMOS. Measurement results show the proposed ADPLL locks in 7 cycles and provides output frequencies ranging from 460.1 MHz to 6.117 GHz.",
author = "Chen, {Yi Wei} and Hao-Chiao Hong",
year = "2014",
month = jan,
day = "1",
doi = "10.1109/ISCAS.2014.6865340",
language = "English",
isbn = "9781479934324",
series = "Proceedings - IEEE International Symposium on Circuits and Systems",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "1134--1137",
booktitle = "2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014",
address = "United States",
note = "null ; Conference date: 01-06-2014 Through 05-06-2014",
}