A Fast Hysteretic Buck DC-DC Converter with Start-up Overshoot Suppression Technique

Kun-Chun Chang; Chin-Long Wey

doi:10.1109/PrimeAsia.2012.6458627

A Fast Hysteretic Buck DC-DC Converter with Start-up Overshoot Suppression Technique

Kun-Chun Chang, Chin-Long Wey

Department of Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Scopus citations

Abstract

The voltage-mode hysteretic converter is one of ripple-based regulators. The converter has the salient features of fast transient response, good conversion efficiency, and simple architecture. However, the major drawbacks include large voltage ripple caused by propagation delay path and excess overshoot voltage during the start-up period. This paper presents an overshoot suppression technique uses two-phase PMOS transistors to optimize the solution among the overshoot voltage, transistor size, and conversion efficiency. There exists a design trade-offs between start-up overshoot voltage and settling time. Results show that, with the proposed suppression technique, the overshoot voltage is reduced from 340mV to 74.4mV. However, the settling time is increased from 15.1us to 21.74 us.

Original language	English
Title of host publication	Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics
Publisher	IEEE
Pages	56-60
Number of pages	5
DOIs	https://doi.org/10.1109/PrimeAsia.2012.6458627
State	Published - 2012

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title = "A Fast Hysteretic Buck DC-DC Converter with Start-up Overshoot Suppression Technique",

abstract = "The voltage-mode hysteretic converter is one of ripple-based regulators. The converter has the salient features of fast transient response, good conversion efficiency, and simple architecture. However, the major drawbacks include large voltage ripple caused by propagation delay path and excess overshoot voltage during the start-up period. This paper presents an overshoot suppression technique uses two-phase PMOS transistors to optimize the solution among the overshoot voltage, transistor size, and conversion efficiency. There exists a design trade-offs between start-up overshoot voltage and settling time. Results show that, with the proposed suppression technique, the overshoot voltage is reduced from 340mV to 74.4mV. However, the settling time is increased from 15.1us to 21.74 us.",

author = "Kun-Chun Chang and Chin-Long Wey",

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AU - Chang, Kun-Chun

AU - Wey, Chin-Long

PY - 2012

Y1 - 2012

N2 - The voltage-mode hysteretic converter is one of ripple-based regulators. The converter has the salient features of fast transient response, good conversion efficiency, and simple architecture. However, the major drawbacks include large voltage ripple caused by propagation delay path and excess overshoot voltage during the start-up period. This paper presents an overshoot suppression technique uses two-phase PMOS transistors to optimize the solution among the overshoot voltage, transistor size, and conversion efficiency. There exists a design trade-offs between start-up overshoot voltage and settling time. Results show that, with the proposed suppression technique, the overshoot voltage is reduced from 340mV to 74.4mV. However, the settling time is increased from 15.1us to 21.74 us.

AB - The voltage-mode hysteretic converter is one of ripple-based regulators. The converter has the salient features of fast transient response, good conversion efficiency, and simple architecture. However, the major drawbacks include large voltage ripple caused by propagation delay path and excess overshoot voltage during the start-up period. This paper presents an overshoot suppression technique uses two-phase PMOS transistors to optimize the solution among the overshoot voltage, transistor size, and conversion efficiency. There exists a design trade-offs between start-up overshoot voltage and settling time. Results show that, with the proposed suppression technique, the overshoot voltage is reduced from 340mV to 74.4mV. However, the settling time is increased from 15.1us to 21.74 us.

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DO - 10.1109/PrimeAsia.2012.6458627

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BT - Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics

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