A fast algorithm and its VLSI architecture for fractional motion estimation for H.264/MPEG-4 AVC video coding

Yu Jen Wang*, Chao Chung Cheng, Tian-Sheuan Chang

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

51 Scopus citations

Abstract

This paper presents a fast algorithm and its VLSI architecture for H.264 fractional motion estimation. Motivated by the high correlation of cost between neighboring fractional pel position, the proposed algorithm efficiently explores the neighborhood position around the minimum one and thus skips other unlikely ones. Thus, the proposed search pattern and early termination under constant quantization parameter can reduce about 50% of computation complexity compared to that in reference software but only with 0.1-0.2 dB peak signal-to-noise ratio degradation and less than 2% of bit rate increase. The VLSI architecture of the proposed algorithm thus can save 40% of area cost due to only half of the processing elements and save 14 % of searching time when compared with the previous design.

Original languageEnglish
Pages (from-to)578-583
Number of pages6
JournalIEEE Transactions on Circuits and Systems for Video Technology
Volume17
Issue number5
DOIs
StatePublished - 1 May 2007

Keywords

  • H.264/AVC
  • Motion estimation
  • Video coding

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