A dynamic scaling FFT processor for DVB-T applications

Yu Wei Lin*, Hsuan Yu Liu, Chen-Yi Lee

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

104 Scopus citations

Abstract

This paper presents an 8192-point FFT processor for DVB-T systems, in which a three-step radix-8 FFT algorithm, a new dynamic scaling approach, and a novel matrix prefetch buffer are exploited. About 64 K bit memory space can be saved in the 8 K point FFT by the proposed dynamic scaling approach. Moreover, with data scheduling and pre-fetched buffering, single-port memory can be adopted without degrading throughput rate. A test chip for 8 K mode DVB-T system has been designed and fabricated using 0.18-μm single-poly six-metal CMOS process with core area of 4.84 mm2. Power dissipation is about 25.2 mW at 20 MHz.

Original languageEnglish
Pages (from-to)2005-2013
Number of pages9
JournalIEEE Journal of Solid-State Circuits
Volume39
Issue number11
DOIs
StatePublished - 1 Nov 2004

Keywords

  • DVB-T
  • Fast Fourier transform (FFT)
  • Orthogonal frequency division multiplexing (OFDM)

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