A dynamic quality-scalable H.264 video encoder chip

Hsiu Cheng Chang*, Yao Chang Yang, Jia Wei Chen, Ching Lung Su, Cheng An Chien, Jiun-In  Guo, Jinn Shyan Wang

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

2 Scopus citations

Abstract

This paper proposes a dynamic quality-scalable H.264 video encoder that comprises 470Kgates and 13.3Kbytes SRAM using 1P8M 0.13μm CMOS technology. Exploiting parameterized algorithms for motion estimation and intra prediction, the proposed design can dynamically configure the encoding modes with the design trade-off between power consumption and video quality for various video encoding applications. It achieves real-time H.264 video encoding on CIF, D1, and HD720@30fps with 7mW-25mW, 27mW-162mW, and 122mW-183mW power dissipation in different quality modes.

Original languageEnglish
Title of host publicationProceedings of the ASP-DAC 2009
Subtitle of host publicationAsia and South Pacific Design Automation Conference 2009
Pages125-126
Number of pages2
DOIs
StatePublished - 20 Apr 2009
EventAsia and South Pacific Design Automation Conference 2009, ASP-DAC 2009 - Yokohama, Japan
Duration: 19 Jan 200922 Jan 2009

Publication series

NameProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Conference

ConferenceAsia and South Pacific Design Automation Conference 2009, ASP-DAC 2009
CountryJapan
CityYokohama
Period19/01/0922/01/09

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