A dual mode channel decoder for 3GPP2 mobile wireless communications

Chien Ching Lin*, Yen Hsu Shin, Hsie-Chia Chang, Chen-Yi Lee

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

2 Scopus citations

Abstract

This paper presents a turbo and Viterbi decoder single chip for 3GPP2 standard. The turbo decoding with a maximum block length of 20,730 and Viterbi decoding with various coding rates are implemented to provide maximum 4.52Mb/s and 5.26Mb/s data rates respectively. The memory access is reduced by the input caching scheme. And the system complexity is lowered by the efficient interleaver design. This chip is fabricated in a 0.18μm six-metal standard CMOS process, and the measured power dissipation is 83mW while decoding a 3.1Mb/s turbo encoded data stream with six iterations for each block.

Original languageEnglish
Title of host publicationESSCIRC 2004 - Proceedings of the 30th European Solid-State Circuits Conference
EditorsM. Steyaert, C.L. Claeys
Pages483-486
Number of pages4
DOIs
StatePublished - 1 Dec 2004
EventESSCIRC 2004 - Proceedings of the 30th European Solid-State Circuits Conference - Leuven, Belgium
Duration: 21 Sep 200423 Sep 2004

Publication series

NameESSCIRC 2004 - Proceedings of the 30th European Solid-State Circuits Conference

Conference

ConferenceESSCIRC 2004 - Proceedings of the 30th European Solid-State Circuits Conference
CountryBelgium
CityLeuven
Period21/09/0423/09/04

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