A dual-edged triggered explicit-pulsed level converting flip-flop with a wide operation range

Mei Wei Chen, Ming Hung Chang, Pei Chen Wu, Yi Ping Kuo, Chun Lin Yang, Yuan Hua Chu, Wei Hwang

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

In a multiple supply voltage system, the level converters are inserted between two different voltage domains. However, those level converters may cause the propagation delays and power consumption. In order to eliminate the overhead of level conversion, a dual-edged triggered explicit-pulsed level converting flip-flop (DETEP-LCFF) with a wide operation range is proposed. It is composed of a clock pulse generator and a modified differential cascode voltage switch with pass gate (DCVSPG) latch. The clock pulse generator has the symmetric pulse triggering time and holding period helping shorten the D-Q delay. By employed diode-connected PMOS transistors and two NMOS transistor stacked below the diode PMOS transistors, the proposed DETEP-LCFF can be operated from near-threshold region to super-threshold region. It is implemented in TSMC 65nm CMOS technology. It functions correctly across all process corners with a wide input voltage range, from 400mV to 1V. The proposed LCFF has a minimum D-Q delay of 781ps, a setup time of - 610ps, and a power dissipation of 2.3μW when the input voltage is 0.4V.

Original languageEnglish
Title of host publicationProceedings - IEEE 26th International SOC Conference, SOCC 2013
PublisherIEEE Computer Society
Pages92-97
Number of pages6
ISBN (Print)9781479911660
DOIs
StatePublished - 1 Jan 2013
Event26th IEEE International System-on-Chip Conference, SOCC 2013 - Erlangen, Germany
Duration: 4 Sep 20136 Sep 2013

Publication series

NameInternational System on Chip Conference
ISSN (Print)2164-1676
ISSN (Electronic)2164-1706

Conference

Conference26th IEEE International System-on-Chip Conference, SOCC 2013
CountryGermany
CityErlangen
Period4/09/136/09/13

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