In this paper, we present a dynamic domain partition simulation technique for parallel numerical solutions of semiconductor device equations. Based on the adaptive finite volume method, a posteriori error estimation, and monotone iterative algorithm, this dynamic load balancing approach has been successfully developed and implemented on a Linux cluster with message passing interface library. The developed simulator is then applied to calculate the physical characteristics of deep submicron dynamic threshold voltage MOSFET (DTMOS). We simulate DTMOS with two different parallel algorithms: (1) 2D dynamic load balancing for parallel domain decomposition; (2) parallel I-V point simulation. Benchmark results show that a well-designed load balancing simulation can reduce the execution time up to an order of magnitude. Compared with the measured data, the simulated results for a 0.08 μm DTMOS are demonstrated to show the accuracy and efficiency of the method.
- Dynamic load balancing
- Parallel adaptive FVM
- Semiconductor device simulation