A digitally testable Σ - Δ modulator using the decorrelating design-for-digital-testability

Sheng Chuan Liang*, Hao-Chiao Hong

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

3 Scopus citations

Abstract

This paper demonstrates a digitally testable second-order Σ - Δ modulator. The modulator under test (MUT) employs the decorrelating design-for-digital-testability (D 3 T) scheme to provide two operation modes: the normal mode and the digital test mode. In the digital test mode, the input switched-capacitor network of the D 3 T modulator is reconfigured as two sub-digital-to-charge converters (sub-DCCs). Each of the sub-DCCs accepts a Σ - Δ modulated bit-stream as its test stimulus. By repetitively inputting the DCCs with the same Σ - Δ modulated bit-stream but with different delays, the DCCs incorporates with the integrator to generate the analog stimulus in the digital test mode. The analog stimulus is analogous to the result of filtering the bit-stream with a two-nonzero-term FIR decorrelating term. Consequently, the D 3 T MUT suffers less from the undesired shaped noise of the digital stimuli, and achieves better digital test accuracy. Measurement results show that the digital tests present a peak signal-to-noise-and-distortion ratio (SNDR) of 80.1 dB at an oversampling ratio of 128. The SNDR results of the digital tests differ from their conventional analog counterparts by no more than 2 dB except for the -3.2 dBFS test. The analog hardware overhead of the D 3 T MUT only consists of 13 switches.

Original languageEnglish
Article number5352329
Pages (from-to)503-507
Number of pages5
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume19
Issue number3
DOIs
StatePublished - 1 Mar 2011

Keywords

  • Analog-to-digital conversion (ADC)
  • Sigma-Delta modulation
  • built-in self-test (BIST)
  • design-for-testability (DfT)
  • integrated circuit testing
  • mixed-mode circuit

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