A digital BIST methodology for spread spectrum clock generators

Maohsuan Chou*, Jenchien Hsu, Chau-Chin Su

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

2 Scopus citations

Abstract

In this paper, a built-in-self-test methodology for spread-spectrum clock generators is presented. It utilizes a multi-phase phase detector to detect the linearity of the frequency variation and the short-term jitter. The methodology is analyzed and simulated. As an all digital design, the hardware overhead is very small.

Original languageEnglish
Title of host publicationProceedings of the 15th Asian Test Symposium 2006
Pages251-254
Number of pages4
DOIs
StatePublished - 1 Dec 2006
Event15th Asian Test Symposium 2006 - Fukuoka, Japan
Duration: 20 Nov 200623 Nov 2006

Publication series

NameProceedings of the Asian Test Symposium
Volume2006
ISSN (Print)1081-7735

Conference

Conference15th Asian Test Symposium 2006
CountryJapan
CityFukuoka
Period20/11/0623/11/06

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