A digital background calibration technique for pipelined analog-to-digital converters

Hung Chih Liu; Zwei M. Lee; Jieh-Tsorng Wu

doi:10.1109/ISCAS.2003.1205705

A digital background calibration technique for pipelined analog-to-digital converters

Hung Chih Liu^*, Zwei M. Lee, Jieh-Tsorng Wu

^*Corresponding author for this work

Department of Electronics Engineering

Research output: Contribution to journal › Conference article › peer-review

8 Scopus citations

Abstract

A new background calibration technique for pipelined analog-to-digital converters is proposed. By dividing the step sizes of the multiplying digital-to-analog converter (MDAC) in a pipeline stages and injecting a random signal into the MDAC, it is possible to calibrate a pipeline stage without interrupting the normal analog-to-digital operation. The calibration can eliminate the nonlinear effects due to the MDAC's gain error, input offset voltage, and output errors in the digital-to-analog conversion.

Original language	English
Journal	Proceedings - IEEE International Symposium on Circuits and Systems
Volume	1
DOIs	https://doi.org/10.1109/ISCAS.2003.1205705
State	Published - 14 Jul 2003
Event	Proceedings of the 2003 IEEE International Symposium on Circuits and Systems - Bangkok, Thailand Duration: 25 May 2003 → 28 May 2003

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abstract = "A new background calibration technique for pipelined analog-to-digital converters is proposed. By dividing the step sizes of the multiplying digital-to-analog converter (MDAC) in a pipeline stages and injecting a random signal into the MDAC, it is possible to calibrate a pipeline stage without interrupting the normal analog-to-digital operation. The calibration can eliminate the nonlinear effects due to the MDAC's gain error, input offset voltage, and output errors in the digital-to-analog conversion.",

author = "Liu, {Hung Chih} and Lee, {Zwei M.} and Jieh-Tsorng Wu",

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AU - Liu, Hung Chih

AU - Lee, Zwei M.

AU - Wu, Jieh-Tsorng

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Y1 - 2003/7/14

N2 - A new background calibration technique for pipelined analog-to-digital converters is proposed. By dividing the step sizes of the multiplying digital-to-analog converter (MDAC) in a pipeline stages and injecting a random signal into the MDAC, it is possible to calibrate a pipeline stage without interrupting the normal analog-to-digital operation. The calibration can eliminate the nonlinear effects due to the MDAC's gain error, input offset voltage, and output errors in the digital-to-analog conversion.

AB - A new background calibration technique for pipelined analog-to-digital converters is proposed. By dividing the step sizes of the multiplying digital-to-analog converter (MDAC) in a pipeline stages and injecting a random signal into the MDAC, it is possible to calibrate a pipeline stage without interrupting the normal analog-to-digital operation. The calibration can eliminate the nonlinear effects due to the MDAC's gain error, input offset voltage, and output errors in the digital-to-analog conversion.

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U2 - 10.1109/ISCAS.2003.1205705

DO - 10.1109/ISCAS.2003.1205705

M3 - Conference article

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JO - Proceedings - IEEE International Symposium on Circuits and Systems

JF - Proceedings - IEEE International Symposium on Circuits and Systems

SN - 0271-4310

Y2 - 25 May 2003 through 28 May 2003

ER -

A digital background calibration technique for pipelined analog-to-digital converters

Abstract

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