A digital background calibration technique for pipelined analog-to-digital converters

Hung Chih Liu*, Zwei M. Lee, Jieh-Tsorng Wu

*Corresponding author for this work

Research output: Contribution to journalConference articlepeer-review

8 Scopus citations

Abstract

A new background calibration technique for pipelined analog-to-digital converters is proposed. By dividing the step sizes of the multiplying digital-to-analog converter (MDAC) in a pipeline stages and injecting a random signal into the MDAC, it is possible to calibrate a pipeline stage without interrupting the normal analog-to-digital operation. The calibration can eliminate the nonlinear effects due to the MDAC's gain error, input offset voltage, and output errors in the digital-to-analog conversion.

Original languageEnglish
JournalProceedings - IEEE International Symposium on Circuits and Systems
Volume1
DOIs
StatePublished - 14 Jul 2003
EventProceedings of the 2003 IEEE International Symposium on Circuits and Systems - Bangkok, Thailand
Duration: 25 May 200328 May 2003

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