A Digital Background Calibration Scheme for Pipelined ADCs Using Multiple-Correlation Estimation

Meng Shuan Wu, Hao-Chiao Hong

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

This paper proposes a digital background calibration scheme for calibrating the linear and the third-order nonlinear gain errors of the residue amplifiers (RAs) in pipelined ADCs. It is based on a novel multiple-correlation estimation (MCE) technique. We define two correction parameters relating to the gain errors of the RA under calibration. By alternately injecting two bi-level pseudo-random signals with designated amplitudes to the RA through the sub-DAC, the desired correction parameters are estimated according to the correlations of the backend ADC's outputs and the injected pseudo-random signals. Two least-mean-square (LMS) loops are adopted to find and to track the optimal values of the correction parameters. Simulation results of a 12-bit pipelined ADC show that the SNDR is improved from 46.4 dB to 73.4 dB with the help of the proposed calibration design. The proposed calibration scheme has the advantages of simple implementation, no restriction on the input signal of the ADC, fast settling, and running in background.

Original languageEnglish
Title of host publication2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781538648810
DOIs
StatePublished - 26 Apr 2018
Event2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Florence, Italy
Duration: 27 May 201830 May 2018

Publication series

NameProceedings - IEEE International Symposium on Circuits and Systems
Volume2018-May
ISSN (Print)0271-4310

Conference

Conference2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018
CountryItaly
CityFlorence
Period27/05/1830/05/18

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