A development and validation platform for communication SOC design

Yu Chen Sun*, Ching-Yao Huang

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Abstract

This paper introduces a development and validation platform that combines hardware modeling and communication system simulation. This platform enables the use of a single platform for multiple purposes throughout a communication system design, including system simulation, software development and hardware modeling. Besides providing cycle accuracy hardware model, the platform is integrated with a multi-device simulation environment. Based on the platform, designers could complete protocol analysis and system simulation in a single stage. The platform is useful for the designs of communication components whose behaviors are highly coupled with transmission medium and other parallel components. In this paper, we will present the basic components and their design strategies.

Original languageEnglish
Title of host publicationAPCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems
Pages101-104
Number of pages4
DOIs
StatePublished - 1 Dec 2006
EventAPCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems - , Singapore
Duration: 4 Dec 20066 Dec 2006

Publication series

NameIEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS

Conference

ConferenceAPCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems
CountrySingapore
Period4/12/066/12/06

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