A design-for-verification technique for functional pattern reduction

Chien-Nan Liu, I. Ling Chen, Jing Yang Jou*

*Corresponding author for this work

Research output: Contribution to journalArticle

3 Scopus citations

Abstract

A design-for-verification (DFV) technique for functional pattern reduction was discussed. It was suggested that applying similar ideas to functional verification could enable an increase in simulation coverage and reduce verification time by the insertion of some DFV points into hardware description level (HDL) designs. The results showed that the number of hard-to-control (HTC) register nodes and the number of selected nodes were not always the same.

Original languageEnglish
Pages (from-to)48-55
Number of pages8
JournalIEEE Design and Test of Computers
Volume20
Issue number2
DOIs
StatePublished - 1 Mar 2003

Fingerprint Dive into the research topics of 'A design-for-verification technique for functional pattern reduction'. Together they form a unique fingerprint.

  • Cite this