A design flow for multiplierless linear-phase fir filters: From system specification to verilog code

Kai Yuan Jheng*, Shyh-Jye Jou, An Y. Wu

*Corresponding author for this work

Research output: Contribution to journalConference articlepeer-review

21 Scopus citations

Abstract

This paper presents a design flow for the multiplierless linear-phase FIR filter synthesizer, which combines several research efforts. We propose a local search algorithm with variable filter order to reduce the number of adders further. In addition, several design techniques are adopted to reduce the hardware complexity of the system. By using this synthesizer, the system designers can design a filter efficiently and a chip can be successfully finished in a very short time.

Original languageEnglish
JournalProceedings - IEEE International Symposium on Circuits and Systems
Volume5
DOIs
StatePublished - 6 Sep 2004
Event2004 IEEE International Symposium on Cirquits and Systems - Proceedings - Vancouver, BC, Canada
Duration: 23 May 200426 May 2004

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