A Design Flow for Micro Bump and Stripe Planning on Modern Chip-Package Co-Design

Ming Yu Huang, Hung-Ming Chen, Kuan Neng Chen, Shih Hsien Wu, Yu Min Lee, An Yu Su

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

Micro bumps and stripes play essential roles for the transmission of signals and the preservation of power integrity in the modern flip-chip packaging process. For different placement block designs on a chip, the best micro bump arrangement and stripe generation method is usually varied accordingly. It often takes a lot of manpower and time cost in generating the delivery path of signal and power transmission in a package. As a result, we propose a way that can automatically generate a power delivery network (PDN) on the top metal layers in a chip and set the coordinate of micro bumps. It can solve the IR drop problem in the early stage, and decrease the integrated circuit (IC) and packaging layout design iteration, thus shorten time-to-market (TTM). Experimental results show that our flows can reduce IR drop to 5% of supply voltage in block.

Original languageEnglish
Title of host publicationProceedings - IEEE 70th Electronic Components and Technology Conference, ECTC 2020
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages2236-2241
Number of pages6
ISBN (Electronic)9781728161808
DOIs
StatePublished - Jun 2020
Event70th IEEE Electronic Components and Technology Conference, ECTC 2020 - Orlando, United States
Duration: 3 Jun 202030 Jun 2020

Publication series

NameProceedings - Electronic Components and Technology Conference
Volume2020-June
ISSN (Print)0569-5503

Conference

Conference70th IEEE Electronic Components and Technology Conference, ECTC 2020
CountryUnited States
CityOrlando
Period3/06/2030/06/20

Keywords

  • flip chip
  • IR drop
  • k-means clustering
  • micro bump
  • power delivery network

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