A decorrelating design-for-digital-testability scheme for Σ-Δ modulators

Hao-Chiao Hong*, Sheng Chuan Liang

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

16 Scopus citations

Abstract

This paper presents a novel decorrelating design-for-digital-testability (D 3T)scheme for Σ-Δ modulators to enhance the test accuracy of using digital stimuli. The input switched-capacitor network of the modulator under test is reconfigured as two or more subdigital-to-charge converters in the test mode. By properly designing the digital stimuli, the shaped noise power of the digital stimulus can be effectively attenuated. As a result, the shaped noise correlation as well as the modulator overload issues are alleviated, thus improving the test accuracy. A second-order Σ-Δ modulator design is used as an example to demonstrate the effectiveness of the proposed scheme. The behavioral simulation results showed that, when the signal level of the stimulus tone is less than - 5 dBFS, the signal-to-noise ratios obtained by the digital stimuli are inferior to those obtained by their analog counterparts of no more than 1.8 dB. Circuit-simulation results also demonstrated that the D 3T scheme has the potential to test moderate nonlinearity. The proposed D 3 scheme has the advantages of achieving high test accuracy, low circuit overhead, high fault observability, and the capability of conducting at-speed tests.

Original languageEnglish
Pages (from-to)60-73
Number of pages14
JournalIEEE Transactions on Circuits and Systems I: Regular Papers
Volume56
Issue number1
DOIs
StatePublished - 26 Feb 2009

Keywords

  • Analog digital conversion
  • Built in self test
  • Built-in self-test (BIST)
  • CMOS mixed mode circuits
  • CMOS mixed-mode circuits
  • Design for testability
  • Design-for-testability (DFT)
  • Integrated circuit testing
  • Integrated-circuit testing
  • Sigma-delta modulation
  • Sigma-Delta modulation

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