A data driven hybrid computer architecture

Chien-Chao Tseng*, Chih Zong Lin, Jiunn Kai Hwang, Kuo Tai Lin

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

Abstract

The combination of dataflow and von Neumann execution models is a recent trend in designing high speed computers. In this paper, a data-driven hybrid computer architecture is presented. Dynamic data-driven execution principle, instead of program counter, is used to control the execution of instructions in a von Neumann style pipelined architecture. Unlike normal dynamic dataflow architecture, data are explicitly stored in memory and their memory locations are used as tags. Matching operation is accomplished by a simple comparison of two counters and no special matching unit is required. With an ideal memory system, no bubble may occur in the pipe if sufficient parallelism exists in the program. Furthermore, multiple memory modules and short-circuit scheme are used to fulfill simultaneous memory requests. An extensive simulator has been designed to evaluate the proposed architecture. The experimental results show that the proposed architecture is promising.

Original languageEnglish
Pages (from-to)89-96
Number of pages8
JournalMicroprocessing and Microprogramming
Volume35
Issue number1-5
DOIs
StatePublished - 1 Jan 1992

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