In this paper, a TCAD-simulation-based optimization methodology for nanoscale CMOS device fabrication is advanced. Electrical characteristics fluctuation is considered and minimized in the optimization process. Integration of device and process simulation is performed to evaluate device performances, where the hybrid intelligent approach enables us to extract optimal recipes which are subject to specified device specification. It is known that production of CMOS devices now are in the sub-65 nm region; therefore, electrical characteristics fluctuation should be simultaneously considered when we extract a set of optimal process parameters. Verification of the efficiency and accuracy of the proposed computational methodology is tested and performed on a 65 nm CMOS device. Compared with realistic fabricated and measured data, this approach achieves the performance of on-target design; in the meanwhile, it significantly reduces the threshold voltage fluctuation. We believe this approach provides a novel way to accelerate the tuning of process parameters and benefit technology of nanodevices.