A cost effective output response analyzer for Σ-δ modulation based BIST systems

Hao-Chiao Hong; Sheng Chuan Liang

doi:10.1109/ATS.2006.261029

A cost effective output response analyzer for Σ-δ modulation based BIST systems

Hao-Chiao Hong^*, Sheng Chuan Liang

^*Corresponding author for this work

National Chiao Tung University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

2 Scopus citations

Abstract

A cost effective output response analyzer (ORA) for Σ-Δ modulation based BIST systems is presented. Instead of using Fast Fourier Transform (FFT) to derive the signal-to-noise-and-distortion ratio (SNDR) in frequency domain, the proposed ORA using the modified controlled sine wave fitting procedure to calculate the signal power and the total-harmonic- distortion-and-noise power in time domain separately. It requires neither parallel multiplier nor complex CPU/DSP and bulky memory thus has a low cost. A second-order design-for-digital-testability Σ-Δ modulator is used as the circuit under test example. Simulation results show that the SNDR differences between conventional FFT analysis and the proposed ORA have a mean and standard deviation of 0.64 dB and 0.36 dB respectively. The cost effectiveness and satisfying accuracy features make it suitable for embedded BIST applications.

Original language	English
Title of host publication	Proceedings of the 15th Asian Test Symposium 2006
Pages	255-261
Number of pages	7
DOIs	https://doi.org/10.1109/ATS.2006.261029
State	Published - 1 Dec 2006
Event	15th Asian Test Symposium 2006 - Fukuoka, Japan Duration: 20 Nov 2006 → 23 Nov 2006

Publication series

Name	Proceedings of the Asian Test Symposium
Volume	2006
ISSN (Print)	1081-7735

Conference

Conference	15th Asian Test Symposium 2006
Country	Japan
City	Fukuoka
Period	20/11/06 → 23/11/06

Access to Document

10.1109/ATS.2006.261029

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title = "A cost effective output response analyzer for Σ-δ modulation based BIST systems",

abstract = "A cost effective output response analyzer (ORA) for Σ-Δ modulation based BIST systems is presented. Instead of using Fast Fourier Transform (FFT) to derive the signal-to-noise-and-distortion ratio (SNDR) in frequency domain, the proposed ORA using the modified controlled sine wave fitting procedure to calculate the signal power and the total-harmonic- distortion-and-noise power in time domain separately. It requires neither parallel multiplier nor complex CPU/DSP and bulky memory thus has a low cost. A second-order design-for-digital-testability Σ-Δ modulator is used as the circuit under test example. Simulation results show that the SNDR differences between conventional FFT analysis and the proposed ORA have a mean and standard deviation of 0.64 dB and 0.36 dB respectively. The cost effectiveness and satisfying accuracy features make it suitable for embedded BIST applications.",

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