A cost effective output response analyzer for Σ-δ modulation based BIST systems

Hao-Chiao Hong*, Sheng Chuan Liang

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

2 Scopus citations

Abstract

A cost effective output response analyzer (ORA) for Σ-Δ modulation based BIST systems is presented. Instead of using Fast Fourier Transform (FFT) to derive the signal-to-noise-and-distortion ratio (SNDR) in frequency domain, the proposed ORA using the modified controlled sine wave fitting procedure to calculate the signal power and the total-harmonic- distortion-and-noise power in time domain separately. It requires neither parallel multiplier nor complex CPU/DSP and bulky memory thus has a low cost. A second-order design-for-digital-testability Σ-Δ modulator is used as the circuit under test example. Simulation results show that the SNDR differences between conventional FFT analysis and the proposed ORA have a mean and standard deviation of 0.64 dB and 0.36 dB respectively. The cost effectiveness and satisfying accuracy features make it suitable for embedded BIST applications.

Original languageEnglish
Title of host publicationProceedings of the 15th Asian Test Symposium 2006
Pages255-261
Number of pages7
DOIs
StatePublished - 1 Dec 2006
Event15th Asian Test Symposium 2006 - Fukuoka, Japan
Duration: 20 Nov 200623 Nov 2006

Publication series

NameProceedings of the Asian Test Symposium
Volume2006
ISSN (Print)1081-7735

Conference

Conference15th Asian Test Symposium 2006
CountryJapan
CityFukuoka
Period20/11/0623/11/06

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