A cost-effective latency-aware memory bus for symmetric multiprocessor systems

Jongsun Kim*, Bo-Cheng Lai, Mau-Chung Chang, Ingrid Verbauwhede

*Corresponding author for this work

Research output: Contribution to journalArticle

5 Scopus citations

Abstract

This paper presents how a multicore system can benefit from the use of a latency-aware memory bus capable of dual-concurrent data transfers on a single wire line: Source synchronous CDMA interconnect (SSCDMA-I) has been adopted to implement the memory bus of a shared-memory multicore system. Two types of bus-based homogeneous and heterogeneous multicore systems are modeled and simulated by a cycle-accurate simulation platform. Unlike the conventional time-division multiplexing (TDM) bus-based multicore system that shows degradation in performance as the number of processing cores increases, the proposed SSCDMA bus-based multicore shows higher performance up to 23.1 percent for four cores. The maximum latency of a heterogeneous multicore system with a mix of traffic loads has been reduced up to 78 percent. These results demonstrate that the performance of multicore systems can be improved with less cost and network complexity by reducing the bus contention interferences and by supporting higher concurrency in memory accesses that brings shorter critical word access latency.

Original languageEnglish
Pages (from-to)1714-1719
Number of pages6
JournalIEEE Transactions on Computers
Volume57
Issue number12
DOIs
StatePublished - 1 Jan 2008

Keywords

  • CMP
  • Concurrency
  • DRAM
  • I/O interconnect
  • Memory bus
  • Memory latency
  • Multicore processor
  • SMP

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