A cost effective BIST second-order Σ-Δ modulator

Hao-Chiao Hong*, Sheng Chuan Liang, Hong Chin Song

*Corresponding author for this work

Research output: Contribution to conferencePaperpeer-review

6 Scopus citations

Abstract

This paper demonstrates a cost effective built-in-self-test (BIST) Σ-Δ modulator prototype. The BIST prototype is composed of a design-for-digital-testability second-order Σ-Δ modulator chip and a FPGA which implements the digital BIST functions. The BIST system is based on the modified control sine wave fitting (MCSWF) procedure. Different from the conventional analysis method using Fast Fourier Transform (FFT), this implementation requires neither any parallel multiplier nor complex CPU/DSP and bulky memory. Measurement results show that the BIST prototype gives a signal-to-noise-and-distortion ratio (SNDR) result of 74.3 dB which is within 0.3 dB comparing with the FFT counterpart. The proposed BIST implementation achieves the advantages of compact hardware, high accuracy, and the flexibility of adjusting the stimuli which are important features for BIST applications.

Original languageEnglish
Pages314-319
Number of pages6
DOIs
StatePublished - 5 Sep 2008
Event2008 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, DDECS - Bratislava, Slovakia
Duration: 16 Apr 200818 Apr 2008

Conference

Conference2008 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, DDECS
CountrySlovakia
CityBratislava
Period16/04/0818/04/08

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