This paper demonstrates a cost effective built-in-self-test (BIST) Σ-Δ modulator prototype. The BIST prototype is composed of a design-for-digital-testability second-order Σ-Δ modulator chip and a FPGA which implements the digital BIST functions. The BIST system is based on the modified control sine wave fitting (MCSWF) procedure. Different from the conventional analysis method using Fast Fourier Transform (FFT), this implementation requires neither any parallel multiplier nor complex CPU/DSP and bulky memory. Measurement results show that the BIST prototype gives a signal-to-noise-and-distortion ratio (SNDR) result of 74.3 dB which is within 0.3 dB comparing with the FFT counterpart. The proposed BIST implementation achieves the advantages of compact hardware, high accuracy, and the flexibility of adjusting the stimuli which are important features for BIST applications.
|Number of pages||6|
|State||Published - 5 Sep 2008|
|Event||2008 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, DDECS - Bratislava, Slovakia|
Duration: 16 Apr 2008 → 18 Apr 2008
|Conference||2008 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, DDECS|
|Period||16/04/08 → 18/04/08|