A cordic processor with efficient table-lookup schemes for rotations & on-line scale factor compensations

Jen Chuan Chih*, Kun Lung Chen, Sau-Gee Chen

*Corresponding author for this work

Research output: Contribution to journalConference article

2 Scopus citations

Abstract

In this paper, we improve our previous efficient CORDIC processor design. The improvements consist of two parts: (1) an improved table-lookup rotation scheme with a smaller table than before, and (2) a new efficient on-line tablelookup scheme for scale-factor computations and compensations which is better than the previous non-online design. Combining the improvements with the original efficient rotation angle recoding algorithm and leading-one (or zero) bit detection (for skipping redundant rotations), we obtain a lowiteration and low-complexity CORIDC processor architecture. The design is more efficient than the current designs, especially in the iteration count. Simulation shows that for n-bit results, about only n/4 iterations are required. We also designed a 16- bit CORDIC processor based on 0.25μm UMC process. Its averaged iteration count is only 4.4 including rotation and scale factor compensations, with a total gate count of 5742 and a maximum operating frequency of 250MHz.

Original languageEnglish
Article number1465337
Pages (from-to)3315-3318
Number of pages4
JournalProceedings - IEEE International Symposium on Circuits and Systems
DOIs
StatePublished - 1 Dec 2005
EventIEEE International Symposium on Circuits and Systems 2005, ISCAS 2005 - Kobe, Japan
Duration: 23 May 200526 May 2005

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