@inproceedings{c55dd477fbef4e3286250e89396d37ed,
title = "A controllable low-power dual-port embedded SRAM for DSP processor",
abstract = "In this paper, a low-power embedded memory module is designed for a multi-threaded DSP processor. A co-design of circuit and architecture technique is proposed. The technique includes three circuit schemes: controllable pre-charged bit-line, low voltage bit-line, and controllable data-retention power gating. Because the low-power control signals are generated by the DSP engine, the operating condition of the memory module can be arbitrarily adjusted by using software programming. The integration of low-power dual-port 8KB SRAM and the multi-threaded DSP engine is implemented in TSMC 130nm CMOS technology. By using these techniques, the overall access power reduction of the DSP core is around 15.30%-16.84%.",
author = "Yang, {Hao I.} and Chang, {Ming Hung} and Lin, {Tay Jyi} and Ou, {Shih Hao} and Deng, {Siang Sen} and Chih-Wei Liu and Wei Hwang",
year = "2007",
month = dec,
day = "1",
doi = "10.1109/MTDT.2007.4547610",
language = "English",
isbn = "9781424416561",
series = "Records of the IEEE International Workshop on Memory Technology, Design and Testing",
pages = "27--30",
booktitle = "17th IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2007",
note = "null ; Conference date: 03-12-2007 Through 05-12-2007",
}