A controllable low-power dual-port embedded SRAM for DSP processor

Hao I. Yang; Ming Hung Chang; Tay Jyi Lin; Shih Hao Ou; Siang Sen Deng; Chih-Wei Liu; Wei Hwang

doi:10.1109/MTDT.2007.4547610

A controllable low-power dual-port embedded SRAM for DSP processor

Hao I. Yang^*, Ming Hung Chang, Tay Jyi Lin, Shih Hao Ou, Siang Sen Deng, Chih-Wei Liu, Wei Hwang

^*Corresponding author for this work

Department of Electronics Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

2 Scopus citations

Abstract

In this paper, a low-power embedded memory module is designed for a multi-threaded DSP processor. A co-design of circuit and architecture technique is proposed. The technique includes three circuit schemes: controllable pre-charged bit-line, low voltage bit-line, and controllable data-retention power gating. Because the low-power control signals are generated by the DSP engine, the operating condition of the memory module can be arbitrarily adjusted by using software programming. The integration of low-power dual-port 8KB SRAM and the multi-threaded DSP engine is implemented in TSMC 130nm CMOS technology. By using these techniques, the overall access power reduction of the DSP core is around 15.30%-16.84%.

Original language	English
Title of host publication	17th IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2007
Pages	27-30
Number of pages	4
DOIs	https://doi.org/10.1109/MTDT.2007.4547610
State	Published - 1 Dec 2007
Event	17th IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2007 - Taipei, Taiwan Duration: 3 Dec 2007 → 5 Dec 2007

Publication series

Name	Records of the IEEE International Workshop on Memory Technology, Design and Testing
ISSN (Print)	1087-4852

Conference

Conference	17th IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2007
Country	Taiwan
City	Taipei
Period	3/12/07 → 5/12/07

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Yang, H. I., Chang, M. H., Lin, T. J., Ou, S. H., Deng, S. S., Liu, C-W., & Hwang, W. (2007). A controllable low-power dual-port embedded SRAM for DSP processor. In 17th IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2007 (pp. 27-30). [4547610] (Records of the IEEE International Workshop on Memory Technology, Design and Testing). https://doi.org/10.1109/MTDT.2007.4547610

Yang, Hao I. ; Chang, Ming Hung ; Lin, Tay Jyi ; Ou, Shih Hao ; Deng, Siang Sen ; Liu, Chih-Wei ; Hwang, Wei. / A controllable low-power dual-port embedded SRAM for DSP processor. 17th IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2007. 2007. pp. 27-30 (Records of the IEEE International Workshop on Memory Technology, Design and Testing).

@inproceedings{c55dd477fbef4e3286250e89396d37ed,

title = "A controllable low-power dual-port embedded SRAM for DSP processor",

abstract = "In this paper, a low-power embedded memory module is designed for a multi-threaded DSP processor. A co-design of circuit and architecture technique is proposed. The technique includes three circuit schemes: controllable pre-charged bit-line, low voltage bit-line, and controllable data-retention power gating. Because the low-power control signals are generated by the DSP engine, the operating condition of the memory module can be arbitrarily adjusted by using software programming. The integration of low-power dual-port 8KB SRAM and the multi-threaded DSP engine is implemented in TSMC 130nm CMOS technology. By using these techniques, the overall access power reduction of the DSP core is around 15.30%-16.84%.",

author = "Yang, {Hao I.} and Chang, {Ming Hung} and Lin, {Tay Jyi} and Ou, {Shih Hao} and Deng, {Siang Sen} and Chih-Wei Liu and Wei Hwang",

year = "2007",

month = dec,

day = "1",

doi = "10.1109/MTDT.2007.4547610",

language = "English",

isbn = "9781424416561",

series = "Records of the IEEE International Workshop on Memory Technology, Design and Testing",

pages = "27--30",

booktitle = "17th IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2007",

note = "null ; Conference date: 03-12-2007 Through 05-12-2007",

}

Yang, HI, Chang, MH, Lin, TJ, Ou, SH, Deng, SS, Liu, C-W & Hwang, W 2007, A controllable low-power dual-port embedded SRAM for DSP processor. in 17th IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2007., 4547610, Records of the IEEE International Workshop on Memory Technology, Design and Testing, pp. 27-30, 17th IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2007, Taipei, Taiwan, 3/12/07. https://doi.org/10.1109/MTDT.2007.4547610

A controllable low-power dual-port embedded SRAM for DSP processor. / Yang, Hao I.; Chang, Ming Hung; Lin, Tay Jyi; Ou, Shih Hao; Deng, Siang Sen; Liu, Chih-Wei ; Hwang, Wei.

17th IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2007. 2007. p. 27-30 4547610 (Records of the IEEE International Workshop on Memory Technology, Design and Testing).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - A controllable low-power dual-port embedded SRAM for DSP processor

AU - Yang, Hao I.

AU - Chang, Ming Hung

AU - Lin, Tay Jyi

AU - Ou, Shih Hao

AU - Deng, Siang Sen

AU - Liu, Chih-Wei

AU - Hwang, Wei

PY - 2007/12/1

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N2 - In this paper, a low-power embedded memory module is designed for a multi-threaded DSP processor. A co-design of circuit and architecture technique is proposed. The technique includes three circuit schemes: controllable pre-charged bit-line, low voltage bit-line, and controllable data-retention power gating. Because the low-power control signals are generated by the DSP engine, the operating condition of the memory module can be arbitrarily adjusted by using software programming. The integration of low-power dual-port 8KB SRAM and the multi-threaded DSP engine is implemented in TSMC 130nm CMOS technology. By using these techniques, the overall access power reduction of the DSP core is around 15.30%-16.84%.

AB - In this paper, a low-power embedded memory module is designed for a multi-threaded DSP processor. A co-design of circuit and architecture technique is proposed. The technique includes three circuit schemes: controllable pre-charged bit-line, low voltage bit-line, and controllable data-retention power gating. Because the low-power control signals are generated by the DSP engine, the operating condition of the memory module can be arbitrarily adjusted by using software programming. The integration of low-power dual-port 8KB SRAM and the multi-threaded DSP engine is implemented in TSMC 130nm CMOS technology. By using these techniques, the overall access power reduction of the DSP core is around 15.30%-16.84%.

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A controllable low-power dual-port embedded SRAM for DSP processor

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