A controllable low-power dual-port embedded SRAM for DSP processor

Hao I. Yang*, Ming Hung Chang, Tay Jyi Lin, Shih Hao Ou, Siang Sen Deng, Chih-Wei Liu, Wei Hwang

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Scopus citations

Abstract

In this paper, a low-power embedded memory module is designed for a multi-threaded DSP processor. A co-design of circuit and architecture technique is proposed. The technique includes three circuit schemes: controllable pre-charged bit-line, low voltage bit-line, and controllable data-retention power gating. Because the low-power control signals are generated by the DSP engine, the operating condition of the memory module can be arbitrarily adjusted by using software programming. The integration of low-power dual-port 8KB SRAM and the multi-threaded DSP engine is implemented in TSMC 130nm CMOS technology. By using these techniques, the overall access power reduction of the DSP core is around 15.30%-16.84%.

Original languageEnglish
Title of host publication17th IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2007
Pages27-30
Number of pages4
DOIs
StatePublished - 1 Dec 2007
Event17th IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2007 - Taipei, Taiwan
Duration: 3 Dec 20075 Dec 2007

Publication series

NameRecords of the IEEE International Workshop on Memory Technology, Design and Testing
ISSN (Print)1087-4852

Conference

Conference17th IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2007
CountryTaiwan
CityTaipei
Period3/12/075/12/07

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    Yang, H. I., Chang, M. H., Lin, T. J., Ou, S. H., Deng, S. S., Liu, C-W., & Hwang, W. (2007). A controllable low-power dual-port embedded SRAM for DSP processor. In 17th IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2007 (pp. 27-30). [4547610] (Records of the IEEE International Workshop on Memory Technology, Design and Testing). https://doi.org/10.1109/MTDT.2007.4547610