A continuous-time ΔΣ modulator with a digital technique for excess loop delay compensation

Yi Zhang, Chia-Hung Chen, Tao He, Xin Meng, Gabor C. Temes

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

4 Scopus citations

Abstract

A 3rd-order continuous-time ΔΣ modulator with a highly-digital technique for excess loop delay (ELD) compensation is reported. A digitally controlled reference switching matrix is used to replace the commonly used power-hungry signal adder and extra DAC driving the quantizer. The feedback DAC is embedded in the quantizer, and implemented by a few switches. The proposed technique helps the modulator tolerate excess loop delay up to half a clock period. The modulator achieves an SQNR of 83.3 dB in a 15 MHz signal bandwidth. The use of a 2-bit FIR feedback DAC lowers the jitter-induced noise by about 10 dB. The simulated power consumption of the modulator is 7 mW.

Original languageEnglish
Title of host publication2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages934-937
Number of pages4
ISBN (Print)9781479934324
DOIs
StatePublished - 1 Jan 2014
Event2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014 - Melbourne, VIC, Australia
Duration: 1 Jun 20145 Jun 2014

Publication series

NameProceedings - IEEE International Symposium on Circuits and Systems
ISSN (Print)0271-4310

Conference

Conference2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014
CountryAustralia
CityMelbourne, VIC
Period1/06/145/06/14

Keywords

  • excess loop delay
  • FIR feedback DAC
  • reference switching

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