A computer aided engineering system for memory BIST

Chau-Chin Su, Shih Ching Hsiao, Hau Zen Zhau, Chung Len Lee

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

An integrated memory test system is presented. It includes a reconfigurable memory test module, a test algorithm editor, a memory fault simulator, and a test code generator. For a given memory organization, fault list, and test algorithm, the system automatically reports the fault coverage, generates control assembly codes, and produces circuit net list for test pattern generation. The system has been implemented in 9000 lines of C++ program based on the Microsoft Windows graphic user interface. It has been verified on different test algorithms and memory chips.

Original languageEnglish
Title of host publicationProceedings of the ASP-DAC 2001
Subtitle of host publicationAsia and South Pacific Design Automation Conference 2001
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages492-495
Number of pages4
ISBN (Electronic)0780366336
DOIs
StatePublished - 1 Jan 2001
EventAsia and South Pacific Design Automation Conference 2001, ASP-DAC 2001 - Yokohama, Japan
Duration: 30 Jan 20012 Feb 2001

Publication series

NameProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
Volume2001-January

Conference

ConferenceAsia and South Pacific Design Automation Conference 2001, ASP-DAC 2001
CountryJapan
CityYokohama
Period30/01/012/02/01

Keywords

  • Automatic test pattern generation
  • Automatic testing
  • Built-in self-test
  • Circuit faults
  • Circuit simulation
  • Circuit testing
  • Computational modeling
  • Computer aided engineering
  • System testing
  • Test pattern generators

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